It is well known for one skilled in the art that the fabrication of integrated circuits requires many fabrication steps, starting with structuring a silicon chip for the desired electrical function, e.g., a memory chip or a processor. This process covers deposition steps, photolithography steps, etching steps and other fabrication steps until the desired function is performed. After that, the integrated circuit is finally mounted on a substrate, such as a printed circuit board, and the electrical interconnections between the circuit and the board are carried out at the same time.
This electrical interconnection is often established by wiring or wire bonding. In a final step, the integrated circuit must be provided with a housing, which can be formed by molding a suitable mold compound around the chip so that the sensitive chip is protected against mechanical damage.
Most memory chips must not be exposed to temperatures above 200° C. because of so called retention failures. The result is that the applicable processing technologies and materials for packaging are limited significantly.
An example of a multichip module with stacked semiconductor chips is described in the U.S. patent application publication 2003/0015803 A1, which is incorporated herein by reference. In this publication bond pads on the rim of the chip are connected with bonding pads on a board with bond wires. Another example is described in the German patent publication 102 51 530 A1 and U.S. Patent application publication 2004/0113256 A1, which are incorporated herein by reference. In a stacked memory device, two semiconductor chips are stacked and are each provided with central rows of bond pads and redistribution layers on the top surface of each chip with inner landing pads. The inner landing pads are connected with the bond pads by wire bonding. The redistribution layers are also provided with landing pads on the rim of the chip, each being connected with contact pads at the board by wire bonding. The complete staple is molded with a mold compound so that the two bare chips and the wire loops are enclosed in this encapsulation.
Typically the fabrication of the package is performed before embedding the chip inside the package. Afterwards electrical interconnection of the chip and package by the wire bonding process as described above is followed by over-molding. Such steps are process steps at low temperatures without any influence on the thermal budget.
However, future and some currently available memory products, especially stacked chips require a different packaging method to meet desired performance, cost and reliability. Recent product generations and all known development paths for future products employ packages which are partially fabricated together with the chip. For example, so called “redistribution layers” as mentioned above are electroplated on the surface of a chip. In some cases even the package is completely “built” around the chip. As mentioned before the applicable processing methods are then limited to temperatures below 200° C.